Over the past few years SRAM (static random access memory) based FPGAs (field programmable gate array) have made significant strides in device fabric features, such as support for partial dynamic reconfiguration, immersed IP (intellectual property) components (including embedded Xilinx's DSP48 and Block RAM (BRAM) modules) and design automation tools to take advantage of these features. Their ASIC (application specific integrated circuits) like computational capabilities and post-launch reconfiguration features make them a viable alternative to replace microprocessors as on-board computers.
The caveat is that the sophistication of the design ported on an FPGA depends on the designer exploring the computation nature of target algorithms, the flexibility they need in terms of acceleration, judicious use of classical techniques such as hardware-software partitioning in conjunction with newer methods of on-chip bitstream decompression and relocation.
In one application example, to navigate in space an autonomous spacecraft must accurately estimate its state from noisy measurements. The Kalman filter (KF) processes each of these measurements and returns the optimal estimate of the state and the error covariance. The computational complexity of even the simple linear KF makes it difficult to run the filter efficiently (i.e. fast enough) on traditional on-board microprocessors. KF acceleration approaches use both novel parallel architectures and algorithm enhancements to make the filter more computationally efficient. Hardware implementations of KF have been shown to dramatically improve performance. KFs are composed of basic matrix operations: multiplication, addition, subtraction, and inversion. These operations can be efficiently implemented as systolic arrays (SA), particularly by using the Faddeev algorithm, the benefits of which stem from its regularity, scalability, and its potential for linearity, and small area requirements.
There have been some implementations of linear KFs on FPGAs but these do not address some of the limitations of specific features of the FPGA platform such as microprocessor or memory interfaces. During run-time the system model or requirements may change due to environment changes, sensor/actuator failure, or at scheduled times. Some have proposed reconfigurable systems to handle these situations, however previous approaches uses soft-reconfiguration, which merge the designs of multiple filters. However no KF implementation invokes dynamic reconfiguration of the hardware.